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| Section | Objectives |
|---|---|
| Monitoring, Performance, and Troubleshooting | - System monitoring
|
| Installation and Initial Configuration | - System setup
|
| Data Protection and Availability | - Replication
|
| FlashArray Architecture and Core Concepts | - Storage concepts
|
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NEW QUESTION # 148
An Implementation Engineer has completed a hardware NDU, but after the upgrade, Purity reports a "health not responding" status when running pureadm status.
Before contacting support, which command should the Implementation Engineer run to review a list of possible logged issues?
Answer: D
Explanation:
Executing a Hardware Non-Disruptive Upgrade (HWNDU) is a complex procedure involving the physical removal and replacement of core processing nodes while host I/O continues uninterrupted. Occasionally, after the new controllers are seated, cabled, and initialized, the cluster may fail to fully form a healthy quorum, manifesting as a "health not responding" state during a pureadm status check.
Before immediately escalating the issue to Pure Storage Support, the Implementation Engineer is expected to perform basic, front-line triage to understand exactly what is blocking the system's high-availability formation. The most effective diagnostic tool for this is the puremessage CLI suite.
While the standard puremessage list command displays standard administrative alerts, a controller in a degraded state often suppresses deeper hardware faults or internal cluster mismatch errors from the standard user view. By executing puremessage list --open --hidden , the engineer forces Purity to reveal all active, unresolved alerts, including internal, low-level system faults normally hidden from standard administrator accounts. This output might reveal issues such as a mismatched firmware version on a newly inserted PCIe card, an improperly seated NVRAM module, or a disconnected internal NTB (Non-Transparent Bridge) link.
Armed with this specific error code or fault description, the engineer can either resolve the physical issue immediately or provide the exact fault string to Pure Support, drastically accelerating the time to resolution.
NEW QUESTION # 149
An Implementation Engineer performing an inventory of hardware for an NDU from an FlashArray//X70R2 to an FlashArray //X90R3 and discovers a complete FlashArray//X90R3 was shipped in place of an NDU kit.
What is the minimum hardware the Implementation Engineer should use from this array to complete the NDU?
Answer: B
Explanation:
To complete the Non-Disruptive Upgrade (NDU) from an //X70R2 to an //X90R3 using a fully shipped array, the Implementation Engineer must extract and use the Controllers and NVRAM modules .
* Stateless Architecture: The FlashArray upgrade philosophy allows the chassis and data drives (Data Packs) to remain in place while the compute (controllers) and cache (NVRAM) are swapped.
* Component Compatibility:
* Controllers: The X90R3 controllers provide the upgraded CPU/performance required.
* NVRAM: The NVRAM modules (located in the chassis front or rear slots depending on generation, but logically paired with controller performance) often differ between generations (R2 vs. R3) and performance tiers (70 vs. 90). The X70R2 NVRAM modules are typically not compatible with X90R3 controllers. Therefore, the engineer must swap the NVRAM modules along with the controllers to ensure the write cache is recognized.
* Power Supplies: Both the X70R2 and X90R3 utilize the same high-capacity 1600W Power Supply Units . Unless the existing PSUs are faulty, they do not technically need to be swapped for the system to function, making "Controller and NVRAM" the precise minimum requirement for the logic upgrade.
NEW QUESTION # 150
Which FlashArray//XL DirectMemory Modules (DMMs) configuration condition is true?
Answer: B
Explanation:
FlashArray//XL architectures offer the ability to leverage DirectMemory Modules (DMMs) to drastically accelerate read-intensive workloads. DMMs are specialized drives built on Storage Class Memory (SCM) technologies, such as Intel Optane. They act as a high-speed read cache tier, sitting seamlessly between the array's ultra-fast NVRAM (which handles incoming writes) and the standard DirectFlash Modules (which provide the bulk capacity).
Because the entire purpose of a DirectMemory Module is to provide the absolute lowest read latency possible, physical proximity to the controller's CPUs and direct access to internal PCIe lanes is mandatory. Therefore, DMMs must be installed directly into the primary FlashArray chassis in specifically designated slots.
Installing DMMs into an external DirectFlash Shelf (DFS) is strictly prohibited and physically unsupported.
Routing read-cache traffic across an external NVMe-oF (RoCE) backend fabric-even at 100GbE speeds- would introduce microsecond latency overheads that completely defeat the performance benefits of Storage Class Memory. Furthermore, DMMs share the exact same physical U.2/NVMe drive slot form factor as standard capacity DFMs (making Option C false), and they are supported across multiple array models beyond just the //XL 170 (making Option B false). An Implementation Engineer must strictly validate the chassis population rules before inserting DMMs to ensure the system recognizes the cache tier correctly upon initialization.
NEW QUESTION # 151
An Implementation Engineer performing an inventory of hardware for an NDU from an FlashArray//X70R2 to an FlashArray //X90R3 and discovers a complete FlashArray//X90R3 was shipped in place of an NDU kit. What is the minimum hardware the Implementation Engineer should use from this array to complete the NDU?
Answer: B
Explanation:
To complete the Non-Disruptive Upgrade (NDU) from an //X70R2 to an //X90R3 using a fully shipped array, the Implementation Engineer must extract and use the Controllers and NVRAM modules.
Stateless Architecture: The FlashArray upgrade philosophy allows the chassis and data drives (Data Packs) to remain in place while the compute (controllers) and cache (NVRAM) are swapped.
Component Compatibility:
Controllers: The X90R3 controllers provide the upgraded CPU/performance required.
NVRAM: The NVRAM modules (located in the chassis front or rear slots depending on generation, but logically paired with controller performance) often differ between generations (R2 vs. R3) and performance tiers (70 vs. 90). The X70R2 NVRAM modules are typically not compatible with X90R3 controllers. Therefore, the engineer must swap the NVRAM modules along with the controllers to ensure the write cache is recognized.
Power Supplies: Both the X70R2 and X90R3 utilize the same high-capacity 1600W Power Supply Units. Unless the existing PSUs are faulty, they do not technically need to be swapped for the system to function, making "Controller and NVRAM" the precise minimum requirement for the logic upgrade.
NEW QUESTION # 152
After upgrading Purity during a new installation, which command should an Implementation Engineer run to determine what version of Purity will be loaded at the next boot of the FlashArray?
Answer: A
Explanation:
The command pureboot list is the correct tool to verify which Purity version is designated to load upon the next system reboot.
FlashArray controllers maintain two boot partitions (often referred to as banks) for redundancy and upgrade safety. When an upgrade is performed, the new Purity software image is written to the inactive bank.
Verification: Running pureboot list displays the status of both boot banks (e.g., Primary and Secondary) and explicitly flags which version is "Running" and which is set for "Next Boot." Why it's critical: Just checking the currently running version (using pureversion or purearray list) is insufficient during an upgrade workflow. An engineer must confirm that the boot pointer has successfully switched to the new version before issuing the reboot command. If pureboot list shows the old version as "Next Boot," a reboot would simply reload the current code, indicating the upgrade installation failed or wasn't finalized.
NEW QUESTION # 153
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