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>> FlashArray-Implementation-Specialist測試引擎 <<
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問題 #118
Which cards are required to connect a DirectFlash Shelf to an FlashArray//XLR5?
答案：C
解題說明：
The FlashArray//XL series (specifically the //XLR5 in this context) utilizes a 100 Gigabit Ethernet-based back-end fabric to communicate with DirectFlash Shelves (DFS). This connection relies on the RoCE (RDMA over Converged Ethernet) protocol to ensure low-latency access to the external NVMe modules.
The specific PCIe interface card validated for this connectivity is often labeled in the Bill of Materials (BOM) or configuration guides as the 2-Port 100GbE iSCSI/RoCE card (or simply the 100GbE Ethernet/RoCE card depending on the specific firmware/labeling revision). Crucially, it must be a 100GbE capability card.
The //XL platform standardized on 100GbE for its shelf interconnects, moving away from the 50GbE used in some previous generations of the //X series. The 200GbE cards are typically reserved for high-speed host connectivity or clustering, not the standard shelf loop. Therefore, ensuring the BOM includes the correct 100GbE RoCE-capable cards is essential for successful shelf detection and operation during installation.
問題 #119
A customer would like to reduce SafeMode settings for retention and eradication with their current policy.
How is authorization obtained to make the requested changes?
答案：C
解題說明：
Reducing SafeMode retention and eradication settings requires approval from two designated SafeMode approvers via Pure1's step-up authentication to ensure secure and authorized policy changes.
問題 #120
The Pure Engagement Request (PER) specifies that iSCSI ports ETH2 and ETH3 should be set to 10 Gb/s.
After configuring the ports and connecting them to the SAN, the Implementation Engineer observes that ETH2
/3 are not negotiating and display 0 b/s. The SAN is operating at 40 Gb/s, with support for up to 100 Gb/s.
What should the Implementation Engineer do to resolve this issue and complete the install?
答案：D
解題說明：
When deploying Ethernet-based storage protocols like iSCSI or NVMe/TCP, establishing a healthy Layer 1 physical connection is the absolute first step. On standard Pure Storage FlashArray controllers (like the //X50 or //X70), the default on-board high-speed ports (ETH2 and ETH3) utilize SFP28 physical cages. These specific ports are hardware-designed to support 10GbE or 25GbE speeds depending on the inserted SFP+ or SFP28 transceiver.
In this scenario, a fundamental physical layer mismatch is occurring. The array ports are attempting to link at
10 Gb/s (using SFP+ optics), but the upstream SAN switch is operating natively at 40 Gb/s (which utilizes a physically larger QSFP+ form factor with four parallel 10G lanes). Auto-negotiation across mismatched optical form factors and lane architectures will almost always fail, resulting in a dead link showing 0 b/s.
An Implementation Engineer cannot magically "force negotiate" a 10G/25G SFP28 port on the array to run at
40G because the physical hardware simply does not support that bandwidth or encoding. Attempting to force the switch side (Option C) will also fail if the physical media doesn't match. The only correct, supported resolution is a hardware intervention: the engineer must replace the transceivers with the appropriate type
. Typically, this involves using a QSFP-to-SFP adapter (QSA) on the switch side, or utilizing a specialized
40G-to-4x10G breakout cable to ensure both ends of the fiber are communicating using the exact same light wavelengths, lane counts, and physical port speeds.
問題 #121
During a HWNDU, the Implementation Engineer initializes CT0 and runs health checks. They observe 12 fewer iSCSI connections compared to pre-upgrade results. While reviewing port speed and status, the output shows CT0.ETH14 at 0.00 b/s. What is the first action the Implementation Engineer should take to troubleshoot?
答案：C
解題說明：
During a hardware upgrade, physical components are often moved or handled, leading to potential connection issues. If a specific port (like CT0.ETH14) that is expected to carry traffic shows 0.00 b/s and "Link Down" or similar status immediately after the controller is initialized, the most likely physical issue is an improperly seated transceiver (SFP) or cable.
The standard troubleshooting hierarchy dictates checking Layer 1 (Physical) first. Therefore, the engineer should ensure the SFP in CT0.ETH14 is fully seated and re-seat it if necessary. SFPs can easily become slightly dislodged during the cable swap from the old controller to the new one. Checking the seating is a quick, non-disruptive step that resolves a high percentage of "dead port" issues during upgrades. Swapping to a management port (Option A) is invalid because management ports often have different speeds or configurations, and asking the customer to reboot hosts (Option B) is premature and potentially disruptive before ruling out the physical array connection.
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問題 #122
What is the required PSU wattage for a FlashArray// X70R2/R3 or X90R2/R3 array?
答案：C
解題說明：
The FlashArray//X70 (R2/R3) and FlashArray//X90 (R2/R3) require 1600W Power Supply Units (PSUs) .
Pure Storage equips its FlashArray//X chassis with different power supply capacities based on the compute load of the installed controllers:
* Performance Tier (X70/X90): These models utilize high-core-count Intel Xeon processors and support the maximum density of NVMe DirectFlash Modules. To support the peak power draw of these components while maintaining N+1 redundancy (where one PSU can support the entire load), the
1600W units are mandatory.
* Entry/Mid Tier (X10/X20/X50): Lower-end models often ship with 1000W or 1200W PSUs (though X50 often uses 1600W in later revisions or specific configs).
* Identification: Implementation Engineers can identify these PSUs by the label on the rear handle (often color-coded or explicitly marked "1600W"). Installing an X90 controller into a chassis with older
1200W PSUs (e.g., during an improper upgrade attempt) would likely trigger a hardware alert or prevent the controllers from booting due to insufficient power budget.
問題 #123
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