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| Certification Vendor: | Pure Storage |
|---|---|
| Exam Name: | Pure Storage Certified FlashArray Implementation Specialist |
| Exam Number: | FAIS |
| Exam Format: | Multiple Choice (three or four options, one to two correct answers) |
| Related Certifications: | Pure Storage FlashArray Implementation Specialist Certification |
| Available Languages: | English |
| Passing Score: | Not publicly disclosed by Pure Storage |
| Exam Duration: | 120 minutes |
| Certificate Validity Period: | 3 years |
| Real Exam Qty: | 75 |
| Exam Price: | USD $300 |
| Sample Questions: | Pure Storage FlashArray-Implementation-Specialist Sample Questions |
| Exam Way: | Online (proctored via examslocal.com) |
| Pre Condition: | Recommended hands-on experience with Pure Storage FlashArray systems. Targeted at internal Pure Storage Support Specialists, Partner Support Specialists with root level access, and Enterprise or Dark Site customers with root level access. |
| Official Syllabus URL: | https://academy.purestorage.com/student/page/2164533-certification-fais |
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NEW QUESTION # 116
Which Purity command can be used to validate I/O is balanced across initiators?
Answer: D
Explanation:
During a post-installation health check or right before initiating a Hardware Non-Disruptive Upgrade (HWNDU), verifying that frontend host multipathing is functioning correctly is arguably the most critical safety procedure an Implementation Engineer performs. If a host is single-pathed or improperly zoned, failing over a controller could trigger an All-Paths-Down (APD) event.
To validate that host traffic is redundant and healthy, the engineer must execute the purehost monitor -- balance command within the Purity CLI.
This powerful diagnostic tool instructs the FlashArray to actively sample incoming read and write SCSI
/NVMe commands across all connected host initiators for a brief period (defaulting to a 5-second interval). It calculates the exact distribution of traffic and displays it as a percentage ("I/O Relative to Max") for each initiator-target path. If a host has Round Robin MPIO configured properly, the output will show traffic flowing evenly across all active paths (e.g., all paths hovering near 90-100% relative to the busiest path). If the output reveals that 100% of the I/O is pinned to a single path while others sit at 0%, the engineer immediately knows there is a zoning or host-side MPIO misconfiguration to address.
NEW QUESTION # 117
An Implementation Engineer is onsite to install a new DFM data pack (DP) to CH0.BAY10-CH0.BAY19 of a FlashArray. After adding the drives to the chassis, which command should the Implementation Engineer run to verify if the new DP is in a wide write group?
Answer: C
Explanation:
To verify the status, presence, and admission of a specific data pack, the correct command is puredrive list --pack CH0.BAY10.
In the context of FlashArray geometry, a "Write Group" (RAID set) is formed by combining DirectFlash Modules. A "Wide Write Group" typically consists of 10 modules (a full data pack). When an engineer installs a standard 10-pack of drives (Bays 10-19), verifying that all 10 drives are successfully recognized and "admitted" confirms that the system has formed the intended wide write group.
The puredrive list command with the --pack argument filters the output to show only the drives in that specific pack. The engineer checks that all 10 drives are listed and their status is "healthy" or "admitted". If fewer drives were admitted (e.g., only 5), it would indicate a "narrow" write group or a hardware issue.
Option A (find_drive.py) is a utility script used to physically locate a drive by blinking its LED, not to check logical RAID configuration.
Option B (puredb list drives) is an internal engineering command (puredb) that is generally not intended for standard field verification and may require root-level access. The puredrive command is the standard CLI tool for this validation.
NEW QUESTION # 118
An Implementation Engineer is performing an inventory for an NDU from a FlashArray//X70R2 to a FlashArray//X70R4 and discovers that a complete FlashArray//X70R4 was shipped instead of an NDU kit.
What is the minimum hardware the Implementation Engineer should use from the new array to complete the NDU?
Answer: B
Explanation:
When performing a hardware non-disruptive upgrade (NDU) from a FlashArray//X70 R2 to a FlashArray
//X70 R4, the Implementation Engineer must understand which components govern the compute upgrade and which house the actual customer data and state. A standard NDU kit for this specific inter-generational upgrade strictly includes the new //XR4 controllers and updated Power Supply Units (PSUs).
The //XR4 controllers utilize significantly more powerful Intel processors and PCIe Gen4 architecture compared to the older //XR2 models. Consequently, they draw considerably more power, necessitating a mandatory upgrade from the older //XR2 PSUs to the higher-wattage units included with the //XR4.
However, the existing NVRAM modules, chassis midplane, and DirectFlash Modules (capacity drives) currently serving data must absolutely remain in place. The legacy NVRAM holds the active, unwritten write cache for the array. If an engineer mistakenly uses the entire shipped //XR4 array (swapping NVRAM modules or migrating drives prematurely without a swing shelf procedure), they risk severe data corruption and an unrecoverable cache loss event. Thus, to safely complete the NDU while preserving data, only the controllers and the power supplies should be harvested from the newly shipped chassis.
NEW QUESTION # 119
An Implementation Engineer runs check start validate-array-health before starting a FlashArray//X70R3 to FlashArray//X70R5 HWNDU and receives code 60 alert indicating an unhealthy NVRAM module in CH0.NVB1. What action Should the Implementation Engineer take to resolve this?
Answer: C
Explanation:
Hardware Non-Disruptive Upgrades (HWNDU) rely strictly on the array being in a fully healthy state before the process begins. The validate-array-health check is designed to gate the upgrade if any component that provides redundancy or data integrity is compromised. NVRAM (Non-Volatile Random Access Memory) modules are critical components in the FlashArray architecture; they store in-flight write data to ensure it is persistent before being destaged to flash.
A "Code 60" alert specifically points to a hardware issue with an NVRAM module. While the //X70 model indeed has redundancy (often using multiple NVRAM modules), proceeding with an upgrade while one is degraded puts the array at risk. During an NDU, controllers reboot and failover; running on reduced redundancy during these critical operations is not supported and is blocked by the health checks.
The correct first step for an Implementation Engineer is to attempt to reseat the unhealthy NVRAM module. Often, connection issues or transient seating faults can trigger these alerts. After reseating, the engineer must run the health check again to confirm the module status has returned to "healthy." If the module remains unhealthy after reseating, it must be replaced before the upgrade can proceed. You cannot simply disable it or ignore it, as the upgrade script will likely refuse to continue to protect data integrity.
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NEW QUESTION # 120
What is the the minimum supported capacity requirement for a FlashArray//XL170R5?
Answer: C
Explanation:
The FlashArray//XL170R5 is a high-performance, high-capacity enterprise storage system. To maintain its performance characteristics and data layout efficiency, Pure Storage enforces a minimum raw capacity requirement for new orders and installations.
For the //XL170R5 model, the minimum supported configuration is 115TB of raw flash. This is typically achieved through a specific population of DirectFlash Modules (e.g., twenty 5.5TB modules or a similar combination that meets the threshold).
Implementation Engineers must verify during the pre-installation site readiness review that the hardware delivered matches this minimum. Attempting to initialize an //XL170 with significantly less capacity (e.g., 90TB) would be an unsupported configuration, potentially leading to performance degradation or an inability to initialize the wide write groups required by the //XL architecture.
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NEW QUESTION # 121
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