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NEW QUESTION # 119
An Implementation Engineer is deploying a FlashArray//XLR5 with two DirectFlash Shelves. The engineer wants to ensure the shelves are installed in the preferred PCIe slots to achieve optimal performance and support.
Which PCIe slots should the Implementation Engineer use for connecting the DFS shelves?
Answer: A
Explanation:
When deploying a high-end Pure Storage FlashArray//XL (which utilizes a massive 5U chassis), the PCIe slot architecture differs significantly from the standard 3U //X series. The //XL is designed for extreme backend NVMe-oF (RoCE) bandwidth to support multiple DirectFlash Shelves (DFS) without creating bottlenecks.
According to the official FlashArray//XL cabling matrix and hardware implementation guides, specific PCIe slots are strictly reserved and optimized for backend expansion. To connect external DirectFlash Shelves, the Implementation Engineer must populate the 100GbE RoCE backend expansion cards into PCIe Slot 0 and PCIe Slot 6 .
When cabling the first two external shelves (typically designated logically as SH8 and SH9 depending on the loop configuration), the preferred mapping routes the NVMe-oF connections from the shelf modules to Slot 0 for one shelf and Slot 6 for the other. Utilizing other slots, such as Slot 1, 7, or 8, is incorrect because those are primarily reserved for frontend host connectivity (like 32G/64G Fibre Channel or frontend NVMe/TCP host bus adapters). Incorrectly slotting the backend cards will result in hardware_check.py validation failures, sub-optimal NUMA node alignment, and potential backend network instability.
NEW QUESTION # 120
Which PCI cards must be validated on the Bill of Materials (BOM) to allow an Implementation Engineer to attach a DirectFlash Shelf to a FlashArray//XL130R5?
Answer: C
Explanation:
The FlashArray//XL series (such as the XL130R5) utilizes a modern backend connectivity architecture for its expansion shelves, specifically the DirectFlash Shelf (DFS). Unlike older generations that might have used SAS (Serial Attached SCSI) for shelf connectivity, the //XL architecture relies on high-speed Ethernet with RoCE (RDMA over Converged Ethernet) to communicate with external media shelves. This ensures that the NVMe drives in the shelf perform with the same low latency as those in the head unit.
To attach a DirectFlash Shelf to a FlashArray//XL130R5, the chassis must be populated with specific PCIe interface cards designated for shelf back-end connectivity. The correct part for this is the FA-XL-100G Ethernet/RoCE 2-Port card. This card provides the necessary 100 Gigabit Ethernet bandwidth and RoCE protocol support required for the NVMe-oF (NVMe over Fabrics) backend fabric that Pure Storage uses.
It is crucial to distinguish this from host-facing cards. While an "iSCSI/RoCE" card exists, the shelf connectivity specifically utilizes the "Ethernet/RoCE" designation in the BOM to differentiate backend fabric ports from frontend host ports. The 200G options are generally reserved for host connectivity or inter-array clustering in specific high-performance setups, but the standard validated card for connecting the DFS to the //XL130R5 is the 100G Ethernet/RoCE adapter. Verifying this line item on the BOM prevents onsite delays where the engineer might otherwise find themselves with incompatible ports for the expansion shelves.
NEW QUESTION # 121
What is the rack unit height of a FlashArray//XR2/3?
Answer: C
Explanation:
The FlashArray//XR2 and //XR3 (representing the FlashArray//X generation) utilize a standardized 3U (3 Rack Units) chassis form factor.
This 3U chassis is the foundation for the majority of the FlashArray//X line, including the //X10, //X20,
//X50, //X70, and //X90 models. It is designed to be compact while providing sufficient airflow and space for the dual controllers, two data packs (up to 20 DirectFlash Modules), and power/cooling infrastructure.
* Dimensions: Approximately 5.12 inches (13 cm) in height.
* Rack Layout: Implementation Engineers must reserve 3U of contiguous space for the base controller chassis. If expansion shelves are included, they typically require an additional 2U each (for SAS or NVMe shelves).
Option B (4U) is not a standard height for current Pure Storage arrays. Option C (5U) refers to the FlashArray//XL , a larger, performance-optimized platform designed for maximum scale and density, which uses a significantly taller chassis to accommodate more expansion slots and power components. Therefore, for the specified R2/R3 X-series, 3U is the correct height.
NEW QUESTION # 122
An Implementation Engineer is performing a FlashArray//XR4 to FlashArray//XL upgrade, and is preparing to remove the XR4 CT0 controller.
Which command should the Implementation Engineer run to stop Purity after confirming CT0 is the secondary controller?
Answer: C
Explanation:
During a complex cross-generational Hardware Non-Disruptive Upgrade (HWNDU) from a FlashArray//XR4 to a FlashArray//XL, the Implementation Engineer must carefully orchestrate the shutdown and removal of the legacy compute nodes. Before physically unlatching and removing the CT0 controller, the Purity//FA operating system processes running on that specific node must be gracefully halted.
Because standard user commands do not allow for this level of low-level service manipulation, the engineer must utilize the purewes (Wessex) command-line suite. Wessex is the internal engineering toolkit used to override high-availability states during hardware replacements.
The correct command to execute is purewes controller disable --purity --verify-mode secondary --verify- array < ARRAY_NAME > ct0 .
This command contains several critical safety mechanisms. The --purity flag specifies that the script should shut down the Purity storage processes rather than just network interfaces. The --verify-mode secondary flag is a mandatory safeguard; it checks the cluster state to guarantee that CT0 has already successfully failed over its active host I/O responsibilities to CT1. If CT0 is still the primary controller, the command will intentionally fail to prevent an accidental storage outage. Finally, --verify-array ensures the engineer is executing this disruptive command on the correct physical array, which is crucial when multiple SSH sessions are open in a busy datacenter.
NEW QUESTION # 123
An Implementation Engineer is installing the first DirectFlash Shelf (DFS) on a FlashArray//XR4 controller. Which ports should the Implementation Engineer use for the connection?
Answer: C
Explanation:
The FlashArray//XR4 utilizes onboard 100GbE RoCE (RDMA over Converged Ethernet) ports for connecting to the first loop of DirectFlash Shelves, removing the need for dedicated PCIe add-in cards for the base configuration. The port mapping for these onboard backend ports differs from previous generations.
On the //XR4 controller chassis, the specific Ethernet interfaces designated for the first DirectFlash Shelf loop are typically the high-numbered onboard ports. In this specific exam context and hardware revision, ETH 18 and ETH 19 are identified as the correct primary backend connectivity ports .
Implementation Engineers must connect the QSFP28 cables from the "uplink" ports on the first shelf (IOM0 and IOM1) to ETH18 and ETH19 on the controllers (CT0 and CT1) respectively. Using incorrect ports (like ETH0/1, which are management) would result in the shelf not being detected by the storage fabric.
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NEW QUESTION # 124
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