NVIDIA NCP-AII復習攻略問題 & NCP-AII過去問無料

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NVIDIA NCP-AII 認定試験の出題範囲:
| トピック | 出題範囲 |
|---|
| トピック 1 | - クラスタのテストと検証:HPLおよびNCCLベンチマークによるクラスタ全体の検証、NVLinkおよびファブリックの帯域幅テスト、ケーブルおよびファームウェアのチェック、HPL、NCCL、NeMoを使用したバーンインテストを網羅しています。
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| トピック 2 | - トラブルシューティングと最適化:GPU、ネットワークカード、電源などの故障したハードウェアコンポーネントの特定と交換、およびAMD
- Intelサーバーとストレージのパフォーマンス最適化について説明します。
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| トピック 3 | - 物理層管理:BlueFieldネットワークプラットフォームデバイスの設定と、AIおよびHPCワークロード向けのマルチインスタンスGPU(MIG)パーティショニングの設定について説明します。
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| トピック 4 | - コントロールプレーンのインストールと構成:ベースコマンドマネージャー、OS、Slurm
- Enroot
- Pyxis、NVIDIA GPUおよびDOCAドライバー、コンテナツールキット、NGC CLIを含むソフトウェアスタックの展開について説明します。
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| トピック 5 | - システムおよびサーバーの立ち上げ:BMC
- OOB
- TPM構成、ファームウェアのアップグレード、ハードウェアのインストール、サーバーがワークロードに対応できる状態であることを確認するための電源および冷却の検証など、GPUベースのAIインフラストラクチャの物理的なセットアップ全体を網羅します。
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>> NVIDIA NCP-AII復習攻略問題 <<
NCP-AII試験の準備方法|100%合格率のNCP-AII復習攻略問題試験|有効的なNVIDIA AI Infrastructure過去問無料
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NVIDIA AI Infrastructure 認定 NCP-AII 試験問題 (Q123-Q128):
質問 # 123
During cluster deployment, the UFM Cable Validation Tool reports " Wrong-neighbor " errors on multiple InfiniBand links. What is the most efficient way to resolve this issue?
- A. Verify LLDP data against topology files and remediate.
- B. Reboot all leaf switches to force LLDP rediscovery.
- C. Disable FEC on all switches to bypass neighbor validation.
- D. Replace all affected cables with higher-grade OM5 fiber optics.
正解:A
解説:
In large-scale InfiniBand fabrics, such as those in NVIDIA DGX SuperPODs, maintaining an exact cabling topology is mandatory for the Adaptive Routing and Fat-Tree algorithms to function correctly. A " Wrong- neighbor " error occurs when the Unified Fabric Manager (UFM) detects that a cable is connected to a port other than the one specified in the master topology map (often a .csv or .topology file). UFM uses LLDP (Link Layer Discovery Protocol) or Subnet Management packets to identify the GUIDs on both ends of a link.
The most efficient remediation is to cross-reference the live LLDP data provided by UFM with the intended design. This allows the engineer to identify if the error is a physical mis-cabling (swapped ports) or a logical error in the topology file. Rebooting switches (Option A) will not fix a physical patch error, and disabling FEC (Option D) would lead to catastrophic signal loss on 400G (NDR) links without addressing the underlying routing logic issue. Correcting the physical patch or updating the topology file ensures the fabric ' s " Ground Truth " is restored.
質問 # 124
You have an NVIDIAAIOO GPU and need to configure it for optimal performance across two distinct AI workloads: a large language model (LLM) training job and a computer vision inference service. The LLM benefits from maximum memory bandwidth, while the inference service requires low latency and high throughput. Which MIG configuration would best suit this scenario?
- A. Create one log. 120gb instance for the LLM and one 4g.40gb instance for inference.
- B. Create two 7g.80gb MIG instances, one for each workload.
- C. Create a single full-GPU instance and use Kubernetes resource quotas to isolate the workloads.
- D. Create one 14g.160gb MIG instance for the LLM and use CUDA MPS to multiplex the inference service.
- E. Utilize Time-Slicing on a single full-GPU instance, allocating specific time slots to each workload using NVIDIA Vgpu technology
正解:A
解説:
Creating a log. 120gb instance for the memory-intensive LLM and a 4g.40gb instance for the inference service provides dedicated resources that cater to the specific needs of each workload, without the overhead or limitations of CUDA MPS or Kubernetes resource quotas. Option A is too conservative, potentially limiting the LLM performance. Option B sacrifices dedicated resources for inference, which may hurt latency. Option C does not leverage MIG and does not guarantee resource isolation and performance consistency. Option E introduces complexities associated with Time-Slicing and might not be suitable for real-time processing.
質問 # 125
You are deploying a multi-GPU server for deep learning training. After installing the GPUs, the system boots, but 'nvidia-smi' only detects one GPU. The motherboard has multiple PCle slots, all of which are physically capable of supporting GPUs. What is the most probable cause?
- A. The other GPUs are not properly seated in their PCle slots. Reseat the GPUs and ensure they are securely connected.
- B. The NVIDIA drivers are not installed correctly or are incompatible with the GPUs. Reinstall the drivers and ensure they are compatible with the specific GPU model and CUDA version.
- C. The other GPUs are faulty and need to be replaced. Test each GPU individually to confirm their functionality.
- D. The power supply is not providing enough power to all GPIJs. Upgrade to a higher wattage power supply.
- E. The system BIOS/UEFI is not configured to enable all PCle slots or the PCle lanes are not allocated correctly. Check the BIOS/IJEFI settings to enable all slots and configure the PCle lane allocation (e.g., x16/x8/x8).
正解:E
解説:
Incorrect BIOS/UEFI settings are the most likely cause when GPUs are physically present but not detected. The BIOS controls PCle lane allocation and slot enabling. Reseating GPUs is a good first step, but if the BIOS is misconfigured, it won't resolve the issue. Insufficient power is also a possibility, but BIOS configuration is more common in initial setup.
質問 # 126
Consider an AI server equipped with two NVIDIAAI 00 GPUs interconnected with NVLink. You want to maximize the memory bandwidth available to a CUDA application. You observe that the application's performance doesn't scale linearly with the number of GPUs. Which of the following coding techniques or configurations could potentially improve inter-GPU memory access performance?
- A. Ensure all memory allocations are performed on GPU O to minimize data transfer.
- B. Use CUDA-aware MPl for inter-GPU communication to leverage NVLink.
- C. Employ Unified Memory (I-JM) with prefetching to automatically migrate data between GPUs as needed.
- D. Disable NVLink to force the application to use PCle, which might provide more consistent performance.
- E. Manually manage data transfers between GPUs using 'cudaMemcpyPeer' to exploit NVLink bandwidth. Choose the GPU with more free memory for allocations.
正解:E
解説:
ScudaMemcpyPeer allows explicit, optimized data transfers between GPUs using NVLink. Unified Memory with prefetching can simplify development, but might not always provide the best performance. CUDA-aware MPl is typically used for inter-node communication, not intra-node GPU-GPU. Allocating all memory on one GPU defeats the purpose of multi-GPU acceleration. PCle will be slower than NVLink. Manually managing memory transfers, while complex, gives the programmer the most control over leveraging NVLink bandwidth.
質問 # 127
You're designing a data center network for inference workloads. The primary requirement is high availability. Which of the following considerations are MOST important for your topology design?
- A. Using the cheapest possible switches
- B. Centralized routing
- C. Prioritizing north-south bandwidth over east-west bandwidth
- D. Implementing redundant paths
- E. Minimizing hop count
正解:D、E
解説:
High availability necessitates redundant paths to avoid single points of failure. Minimizing hop count reduces latency and the potential for network congestion. Using cheap switches is detrimental to availability. Inference workloads typically involve both north-south and east-west traffic, but redundant paths and minimizing hop count are most crucial for availability. Centralized routing can be a single point of failure and is generally less resilient than distributed routing.
質問 # 128
......
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