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| Certification Vendor: | Pure Storage |
|---|---|
| Exam Name: | Pure Storage Certified FlashArray Implementation Specialist |
| Exam Number: | FAIS |
| Certificate Validity Period: | 3 years |
| Exam Duration: | 120 minutes |
| Exam Format: | Multiple Choice (three or four options, one to two correct answers) |
| Passing Score: | Not publicly disclosed by Pure Storage |
| Related Certifications: | Pure Storage FlashArray Implementation Specialist Certification |
| Exam Price: | USD $300 |
| Available Languages: | English |
| Real Exam Qty: | 75 |
| Sample Questions: | Pure Storage FlashArray-Implementation-Specialist Sample Questions |
| Exam Way: | Online (proctored via examslocal.com) |
| Pre Condition: | Recommended hands-on experience with Pure Storage FlashArray systems. Targeted at internal Pure Storage Support Specialists, Partner Support Specialists with root level access, and Enterprise or Dark Site customers with root level access. |
| Official Syllabus URL: | https://academy.purestorage.com/student/page/2164533-certification-fais |
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NEW QUESTION # 116
An Implementation Engineer is getting ready to install four DFMs into a 16-module efficiency bundle and notices that the new modules are DFMDs while the installed modules are DFMs. What should the Implementation Engineer do to get the array using a 20-module Wide write group?
Answer: B
Explanation:
FlashArray performance and capacity efficiency are optimized when drives are grouped into "Wide Write Groups" (typically 20 modules). Purity OS generally enforces strict homogeneity within a write group to ensure consistent performance and reliability. Specifically, mixing standard DirectFlash Modules (DFM) with DirectFlash Modules with Distributed NVRAM (DFMD) in the same write group is restricted by default because of the architectural differences in how they handle persistent memory and I/O acknowledgment.
However, in upgrade scenarios where a customer is expanding an existing 16-module DFM group to a 20- module group using newer DFMD spares or expansion packs, Purity includes an engineering tunable to permit this mixed configuration. The correct procedure is to physically install the new DFMDs and run the admission command. Because of the mix, the array might initially hesitate or create a separate group. To force the creation of a single 20-drive Wide Write Group (WWG) , the Implementation Engineer must work with Pure Storage Support to apply the specific tunable puretune --set ALLOW_DFMD_IN_DFM_WWG 1 .
This overrides the default restriction, allowing the system to merge the disparate module types into a single, high-efficiency capacity pool.
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NEW QUESTION # 117
An Implementation Engineer is installing the first DirectFlash Shelf (DFS) on a FlashArray//XR4 controller.
Which ports should the Implementation Engineer use for the connection?
Answer: A
Explanation:
The FlashArray//XR4 utilizes onboard 100GbE RoCE (RDMA over Converged Ethernet) ports for connecting to the first loop of DirectFlash Shelves, removing the need for dedicated PCIe add-in cards for the base configuration. The port mapping for these onboard backend ports differs from previous generations.
On the //XR4 controller chassis, the specific Ethernet interfaces designated for the first DirectFlash Shelf loop are typically the high-numbered onboard ports. In this specific exam context and hardware revision, ETH 18 and ETH 19 are identified as the correct primary backend connectivity ports .
Implementation Engineers must connect the QSFP28 cables from the "uplink" ports on the first shelf (IOM0 and IOM1) to ETH18 and ETH19 on the controllers (CT0 and CT1) respectively. Using incorrect ports (like ETH0/1, which are management) would result in the shelf not being detected by the storage fabric.
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NEW QUESTION # 118
An Implementation Engineer is performing a FlashArray//XR4 to FlashArray//XL upgrade, and is preparing to remove the XR4 CT0 controller.
Which command should the Implementation Engineer run to stop Purity after confirming CT0 is the secondary controller?
Answer: C
Explanation:
During a complex cross-generational Hardware Non-Disruptive Upgrade (HWNDU) from a FlashArray//XR4 to a FlashArray//XL, the Implementation Engineer must carefully orchestrate the shutdown and removal of the legacy compute nodes. Before physically unlatching and removing the CT0 controller, the Purity//FA operating system processes running on that specific node must be gracefully halted.
Because standard user commands do not allow for this level of low-level service manipulation, the engineer must utilize the purewes (Wessex) command-line suite. Wessex is the internal engineering toolkit used to override high-availability states during hardware replacements.
The correct command to execute is purewes controller disable --purity --verify-mode secondary --verify- array < ARRAY_NAME > ct0 .
This command contains several critical safety mechanisms. The --purity flag specifies that the script should shut down the Purity storage processes rather than just network interfaces. The --verify-mode secondary flag is a mandatory safeguard; it checks the cluster state to guarantee that CT0 has already successfully failed over its active host I/O responsibilities to CT1. If CT0 is still the primary controller, the command will intentionally fail to prevent an accidental storage outage. Finally, --verify-array ensures the engineer is executing this disruptive command on the correct physical array, which is crucial when multiple SSH sessions are open in a busy datacenter.
NEW QUESTION # 119
On a FlashArray//X50 R2/R3 Fibre Channel (FC) array, what is the default type and placement of the PCIe FC card?
Answer: B
Explanation:
For the FlashArray//X50 R2 and R3 models, the default Fibre Channel (FC) configuration utilizes a 4-port PCIe Fibre Channel card installed in Slot 0.
The hardware architecture of the FlashArray//X series differentiates slot usage based on the model controller chassis.
FlashArray//X10 and //X20: These lower-end models utilize Slot 2 for host connectivity (Fibre Channel or iSCSI) because Slots 0 and 1 are typically reserved or occupied by onboard controllers/mezzanine cards. The standard card for these models is often a 2-port card.
FlashArray//X50, //X70, and //X90: These mid-to-high-range models feature a different PCIe bus layout. Slot 0 is the primary designated slot for Host I/O connectivity. To support the higher performance capabilities and port density requirements of the X50, Pure Storage defaults to 4-port FC cards (typically 16Gb or 32Gb).
Therefore, identifying the model number is crucial. Since the question specifies the X50 (R2/R3), the correct placement is Slot 0, and the correct card type is the 4-port model. Option A is incorrect because the 2-port card is not the standard default for the performance-tier X50. Option B describes the configuration for an X20, not an X50.
NEW QUESTION # 120
After racking a new FlashArray with one data pack, how should DirectFlash modules be installed?
Answer: A
Explanation:
Proper airflow and thermal management are critical for the reliability of high-density storage arrays. FlashArray chassis are designed with specific airflow baffles and cooling zones that rely on the drive bays being populated in a specific order.
When installing a new FlashArray with a single data pack (typically 10 drives), the Implementation Engineer must install the DirectFlash Modules starting in bay 0, filling from left to right.
Bay 0 is typically the leftmost slot (when facing the front of the array).
Filling slots 0-9 ensures that the first "cooling zone" is properly pressurized, forcing air through the populated modules and the chassis midplane correctly.
Leaving gaps (e.g., installing in slots 10-19 while 0-9 are empty) can disrupt the airflow path, potentially leading to hotspots or inefficient cooling for the controllers behind the backplane.
Additionally, the software enumeration of drives often expects contiguous population starting from the lowest index for logical clarity, though cooling is the primary physical constraint.
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NEW QUESTION # 121
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