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| Certification Vendor: | Pure Storage |
|---|---|
| Exam Name: | Pure Storage Certified FlashArray Implementation Specialist Exam |
| Exam Number: | FlashArray-Implementation-Specialist |
| Related Certifications: | Pure Storage Certified FlashArray Storage Professional Pure Storage Certified FlashArray Support Specialist |
| Exam Price: | $300 USD |
| Real Exam Qty: | 60-75 |
| Available Languages: | English |
| Exam Duration: | 120 minutes |
| Exam Format: | Scenario-based questions, Multiple choice |
| Certificate Validity Period: | 3 years |
| Passing Score: | 70% |
| Recommended Training: | Pure Academy - FlashArray Implementation Specialist Prep Course FlashArray Implementation Specialist Study Guide |
| Exam Registration: | Pure Storage Certification Portal |
| Sample Questions: | Pure Storage FlashArray-Implementation-Specialist Sample Questions |
| Exam Way: | Online proctored exam / Authorized test center |
| Pre Condition: | Recommended: 3–5 years storage industry experience, 6–12 months Pure Storage experience; no mandatory prerequisites |
| Official Syllabus URL: | https://www.purestorage.com/uk/services/certifications/flasharray-implementation-specialist.html |
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NEW QUESTION # 167
During an intra-series upgrade from //XR3 to //XR4, which command should the Implementation Engineer run to verify host connectivity before removing the secondary controller?
Answer: B
Explanation:
Executing an intra-series Hardware Non-Disruptive Upgrade (HWNDU) from a FlashArray//XR3 to an //XR4 is a highly orchestrated procedure. It involves failing over active I/O responsibilities, physically removing legacy controller nodes, and seamlessly introducing newer generation hardware without causing any downtime for the connected hosts.
Before an Implementation Engineer physically unplugs or removes a secondary controller-or initiates a failover to take the primary controller offline-it is an absolute prerequisite to verify that the frontend host multi-pathing is healthy. If a host is accidentally single-pathed to the controller that is about to be removed, an all-paths-down (APD) event will occur, causing immediate application disruption.
To safely validate this from the array's perspective, the engineer must execute the iobalance --sampletime 30 command within the Purity CLI. This specialized diagnostic command forces the array to actively sample and monitor the incoming SCSI/NVMe read and write commands across all frontend target ports for a continuous
30-second window. The output produces a detailed matrix showing exactly how traffic is distributed across both controllers and all active host initiators. If the data confirms that I/O is cleanly balanced and redundantly flowing across the surviving controller's paths, the engineer can confidently proceed with the physical removal phase of the HWNDU.
NEW QUESTION # 168
What is the rack unit height of a FlashArray//XL?
Answer: A
Explanation:
The FlashArray//XL features a 5 Rack Unit (5U) chassis height.
This form factor represents a significant change from the standard FlashArray//X and //C series, which utilize a 3U chassis. The increase to 5U is engineered to support the massive performance and density requirements of the //XL platform.
* Key Design Features: The 5U height accommodates:
* Dual Controllers: Larger, high-performance controllers with increased airflow requirements.
* 40 DirectFlash Module Slots: Double the drive density of the 3U chassis (which holds 20), allowing for petabytes of effective capacity in the base unit.
* 4 Power Supplies: A 2+2 redundant power architecture.
* 9 PCIe Slots: Extensive I/O expansion for host and backend connectivity.
* Airflow: Dedicated fan modules and thermal ducting to cool the high-wattage components (up to
3.5kW max power draw).
NEW QUESTION # 169
Which PCI cards must be validated on the Bill of Materials (BOM) to allow an Implementation Engineer to attach a DirectFlash Shelf to a FlashArray//XL130R5?
Answer: A
Explanation:
The FlashArray//XL series (such as the XL130R5) utilizes a modern backend connectivity architecture for its expansion shelves, specifically the DirectFlash Shelf (DFS). Unlike older generations that might have used SAS (Serial Attached SCSI) for shelf connectivity, the //XL architecture relies on high-speed Ethernet with RoCE (RDMA over Converged Ethernet) to communicate with external media shelves. This ensures that the NVMe drives in the shelf perform with the same low latency as those in the head unit.
To attach a DirectFlash Shelf to a FlashArray//XL130R5, the chassis must be populated with specific PCIe interface cards designated for shelf back-end connectivity. The correct part for this is the FA-XL-100G Ethernet/RoCE 2-Port card. This card provides the necessary 100 Gigabit Ethernet bandwidth and RoCE protocol support required for the NVMe-oF (NVMe over Fabrics) backend fabric that Pure Storage uses.
It is crucial to distinguish this from host-facing cards. While an "iSCSI/RoCE" card exists, the shelf connectivity specifically utilizes the "Ethernet/RoCE" designation in the BOM to differentiate backend fabric ports from frontend host ports. The 200G options are generally reserved for host connectivity or inter-array clustering in specific high-performance setups, but the standard validated card for connecting the DFS to the //XL130R5 is the 100G Ethernet/RoCE adapter. Verifying this line item on the BOM prevents onsite delays where the engineer might otherwise find themselves with incompatible ports for the expansion shelves.
NEW QUESTION # 170
What are the starter configurations of DFMDs in a Gen 2 DirectFlash Shelf?
Answer: C
NEW QUESTION # 171
What is the minimum supported capacity requirement for a FlashArray//XL170R5?
Answer: A
Explanation:
The Pure Storage FlashArray//XL170 R5 is the highest-tier array in the //XL lineup, engineered specifically for maximum performance density, aggressive OLTP database consolidation, and massive throughput.
Because of its incredibly powerful Intel processors and high-bandwidth PCIe Gen 4 architecture, it demands a specific minimum storage footprint. If an array has too few drives, the backend flash media becomes a bottleneck, effectively starving the controllers of I/O.
According to Pure Storage configuration limits and sizing tools, the minimum supported capacity requirement for an //XL170 R5 chassis is 135TB .
This minimum baseline is typically provisioned using three separate 45TB data packs (represented in official BOM configurations as 135TB-45/45/45/0). The //XL architecture relies exclusively on DirectFlash Modules with Distributed NVRAM (DFMDs). To properly distribute the write cache, maintain N+2 high availability across the flash media, and deliver the extreme IOPS expected of an //XL170, the chassis requires this robust baseline population of DFMDs. Attempting to deploy an //XL170 with a smaller capacity (such as 90TB) violates the performance sizing guidelines. Customers requiring smaller baseline capacities are generally steered toward the FlashArray//XL130 or the //X90 series.
NEW QUESTION # 172
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